Inherits BaudGen, and Shift_REG.
Inherited by UART.
Processes | |
| PROCESS_43 | ( clk , reset ) |
Constants | |
| zeroVect | std_logic_vector ( Data_sz +1 downto 0 ) := ( others = > ' 0 ' ) |
Signals | |
| Bclk | std_logic |
| RDATA_int | std_logic_vector ( Data_sz +1 downto 0 ) |
| WDATA_int | std_logic_vector ( Data_sz +1 downto 0 ) |
| TXD_Dummy | std_logic |
| NwDat_int | std_logic |
| NwDat_int_reg | std_logic |
| receive | std_logic |
Component Instantiations | |
| BaudGenerator | BaudGen <Entity BaudGen> |
| RX_REG | Shift_REG <Entity Shift_REG> |
| TX_REG | Shift_REG <Entity Shift_REG> |
Definition at line 51 of file UART.vhd.
BaudGenerator BaudGen [Component Instantiation] |
NwDat_int_reg std_logic [Signal] |