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This is the complete list of members for ADS7886_drvr, including all inherited members.

AD_in	ADS7886_drvr	`[Port]`
AD_out	ADS7886_drvr	`[Port]`
ChanelCount	ADS7886_drvr	`[Generic]`
clk	ADS7886_drvr	`[Port]`
ADS7886_drvr::ar_ADS7886_drvr.Clk_divider.clk	Clk_divider	`[Port]`
clk_divided	Clk_divider	`[Port]`
clk_int	ar_ADS7886_drvr	`[Signal]`
Clk_divider.clk_int	ar_Clk_divider	`[Signal]`
clk_TRIGER	ar_Clk_divider	`[Constant]`
clkdivider	ar_ADS7886_drvr	`[Component Instantiation]`
clkkHz	ADS7886_drvr	`[Generic]`
cnv	AD7688_spi_if	`[Port]`
cnv_int	ar_ADS7886_drvr	`[Signal]`
cnv_reg	ar_AD7688_spi_if	`[Signal]`
convTrigger	ar_ADS7886_drvr	`[Constant]`
cpt1	ar_Clk_divider	`[Signal]`
DataReady	ADS7886_drvr	`[Port]`
general_purpose	ADS7886_drvr	`[Package]`
i	ar_ADS7886_drvr	`[Signal]`
IEEE	ADS7886_drvr	`[Library]`
ADS7886_drvr::ar_ADS7886_drvr.Clk_divider.IEEE	Clk_divider	`[Library]`
lpp	ADS7886_drvr	`[Library]`
lpp_ad_conv	ADS7886_drvr	`[Package]`
OSC_freqHz	Clk_divider	`[Generic]`
PROCESS_17(reset, clk)	ar_Clk_divider	`[Process]`
PROCESS_23(clk, reset)	ar_AD7688_spi_if	`[Process]`
reset	ADS7886_drvr	`[Port]`
ADS7886_drvr::ar_ADS7886_drvr.Clk_divider.reset	Clk_divider	`[Port]`
sckgen(clk, reset)	ar_ADS7886_drvr	`[Process]`
sdi	AD7688_spi_if	`[Port]`
shift_reg	ar_AD7688_spi_if	`[Signal]`
smplClk	ADS7886_drvr	`[Port]`
smplClk_reg	ar_ADS7886_drvr	`[Signal]`
smpout	ADS7886_drvr	`[Port]`
smpout_int	ar_ADS7886_drvr	`[Signal]`
spidrvr	ar_ADS7886_drvr	`[Component Instantiation]`
STD_LOGIC_1164	ADS7886_drvr	`[Package]`
ADS7886_drvr::ar_ADS7886_drvr.Clk_divider.STD_LOGIC_1164	Clk_divider	`[Package]`
TargetFreq_Hz	Clk_divider	`[Generic]`

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