Top_FifoRead Entity Reference

Programme de la FIFO. More...

Inherits Top_FifoRead::ar_Top_FifoRead.

Inherited by ar_APB_FifoRead, and lpp_memory [private].

List of all members.

Architectures
ar_Top_FifoRead	Architecture
Libraries
IEEE
techmap
Packages
std_logic_1164
numeric_std
gencomp
config
Generics
Data_sz	integer := 16
Addr_sz	integer := 8
addr_max_int	integer := 256
Ports
raz	in std_logic
	Horloge et reset general du composant.
clk	in std_logic
	Horloge et reset general du composant.
flag_RE	in std_logic
	Flag, Demande la lecture de la mémoire.
flag_WR	in std_logic
	Flag, Demande l'écriture dans la mémoire.
Data_in	in std_logic_vector ( Data_sz -1 downto 0 )
	Data en entrée du composant.
Waddr	in std_logic_vector ( Addr_sz -1 downto 0 )
	Adresse du registre d'écriture dans la mémoire.
empty	out std_logic
	Flag, Mémoire vide.
Raddr	out std_logic_vector ( Addr_sz -1 downto 0 )
	Adresse du registre de lecture de la mémoire.
Data_out	out std_logic_vector ( Data_sz -1 downto 0 )
	Data en sortie du composant.

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Detailed Description

Programme de la FIFO.

Definition at line 31 of file Top_FifoRead.vhd.

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Member Data Documentation

addr_max_int integer := 256 [Generic]

Reimplemented in APB_FifoRead.

Definition at line 35 of file Top_FifoRead.vhd.

Addr_sz integer := 8 [Generic]

Reimplemented in APB_FifoRead.

Definition at line 34 of file Top_FifoRead.vhd.

clk in std_logic [Port]

Horloge et reset general du composant.

Reimplemented from Link_Reg.

Reimplemented in APB_FifoRead.

Definition at line 37 of file Top_FifoRead.vhd.

config package [Package]

Definition at line 27 of file Top_FifoRead.vhd.

Data_in in std_logic_vector ( Data_sz -1 downto 0 ) [Port]

Data en entrée du composant.

Definition at line 40 of file Top_FifoRead.vhd.

Data_out out std_logic_vector ( Data_sz -1 downto 0 ) [Port]

Data en sortie du composant.

Reimplemented from Link_Reg.

Definition at line 44 of file Top_FifoRead.vhd.

Data_sz integer := 16 [Generic]

Reimplemented from Link_Reg.

Reimplemented in APB_FifoRead.

Definition at line 33 of file Top_FifoRead.vhd.

empty out std_logic [Port]

Flag, Mémoire vide.

Reimplemented from Link_Reg.

Definition at line 42 of file Top_FifoRead.vhd.

flag_RE in std_logic [Port]

Flag, Demande la lecture de la mémoire.

Reimplemented from Link_Reg.

Definition at line 38 of file Top_FifoRead.vhd.

flag_WR in std_logic [Port]

Flag, Demande l'écriture dans la mémoire.

Reimplemented from Link_Reg.

Definition at line 39 of file Top_FifoRead.vhd.

gencomp package [Package]

Definition at line 26 of file Top_FifoRead.vhd.

IEEE library [Library]

Reimplemented from Link_Reg.

Definition at line 22 of file Top_FifoRead.vhd.

numeric_std package [Package]

Reimplemented from Link_Reg.

Definition at line 24 of file Top_FifoRead.vhd.

Raddr out std_logic_vector ( Addr_sz -1 downto 0 ) [Port]

Adresse du registre de lecture de la mémoire.

Definition at line 43 of file Top_FifoRead.vhd.

raz in std_logic [Port]

Horloge et reset general du composant.

Reimplemented from Link_Reg.

Definition at line 37 of file Top_FifoRead.vhd.

std_logic_1164 package [Package]

Reimplemented from Link_Reg.

Reimplemented in APB_FifoRead, and lpp_memory.

Definition at line 23 of file Top_FifoRead.vhd.

techmap library [Library]

Definition at line 25 of file Top_FifoRead.vhd.

Waddr in std_logic_vector ( Addr_sz -1 downto 0 ) [Port]

Adresse du registre d'écriture dans la mémoire.

Reimplemented in APB_FifoRead.

Definition at line 41 of file Top_FifoRead.vhd.

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The documentation for this class was generated from the following file:

• lpp_memory/Top_FifoRead.vhd