Link_Reg Entity Reference

Programme qui va permettre de "pipeliner" la FIFO, donnée disponible en sortie dé son écriture en entrée de la FIFO. More...

Inherits Link_Reg::ar_Link_Reg.

Inherited by lpp_memory [private], ar_Top_FIFO, and ar_Top_FifoRead.

List of all members.

Architectures
ar_Link_Reg	Architecture
Libraries
IEEE
Packages
std_logic_1164
numeric_std
FIFO_Config
Generics
Data_sz	integer := 16
Ports
raz	in std_logic
	Horloge et reset general du composant.
clk	in std_logic
	Horloge et reset general du composant.
Data_one	in std_logic_vector ( Data_sz -1 downto 0 )
	Donnée en entrée de la FIFO, coté écriture.
Data_two	in std_logic_vector ( Data_sz -1 downto 0 )
	Donnée en sortie de la FIFO, coté lecture.
flag_RE	in std_logic
	Flag, Demande la lecture de la mémoire.
flag_WR	in std_logic
	Flag, Demande l'écriture dans la mémoire.
empty	in std_logic
	Flag, Mémoire vide.
Data_out	out std_logic_vector ( Data_sz -1 downto 0 )
	Donnée en sortie, pipelinée.

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Detailed Description

Programme qui va permettre de "pipeliner" la FIFO, donnée disponible en sortie dé son écriture en entrée de la FIFO.

Definition at line 29 of file Link_Reg.vhd.

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Member Data Documentation

clk in std_logic [Port]

Horloge et reset general du composant.

Reimplemented in APB_FifoRead, and Top_FifoRead.

Definition at line 32 of file Link_Reg.vhd.

Data_one in std_logic_vector ( Data_sz -1 downto 0 ) [Port]

Donnée en entrée de la FIFO, coté écriture.

Definition at line 33 of file Link_Reg.vhd.

Data_out out std_logic_vector ( Data_sz -1 downto 0 ) [Port]

Donnée en sortie, pipelinée.

Reimplemented in Top_FifoRead.

Definition at line 38 of file Link_Reg.vhd.

Data_sz integer := 16 [Generic]

Reimplemented in APB_FifoRead, and Top_FifoRead.

Definition at line 30 of file Link_Reg.vhd.

Data_two in std_logic_vector ( Data_sz -1 downto 0 ) [Port]

Donnée en sortie de la FIFO, coté lecture.

Definition at line 34 of file Link_Reg.vhd.

empty in std_logic [Port]

Flag, Mémoire vide.

Reimplemented in Top_FifoRead.

Definition at line 37 of file Link_Reg.vhd.

FIFO_Config package [Package]

Definition at line 25 of file Link_Reg.vhd.

flag_RE in std_logic [Port]

Flag, Demande la lecture de la mémoire.

Reimplemented in Top_FifoRead.

Definition at line 35 of file Link_Reg.vhd.

flag_WR in std_logic [Port]

Flag, Demande l'écriture dans la mémoire.

Reimplemented in Top_FifoRead.

Definition at line 36 of file Link_Reg.vhd.

IEEE library [Library]

Reimplemented in Top_FifoRead.

Definition at line 22 of file Link_Reg.vhd.

numeric_std package [Package]

Reimplemented in Top_FifoRead.

Definition at line 24 of file Link_Reg.vhd.

raz in std_logic [Port]

Horloge et reset general du composant.

Reimplemented in Top_FifoRead.

Definition at line 32 of file Link_Reg.vhd.

std_logic_1164 package [Package]

Reimplemented in APB_FifoRead, lpp_memory, and Top_FifoRead.

Definition at line 23 of file Link_Reg.vhd.

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The documentation for this class was generated from the following file:

• lpp_memory/Link_Reg.vhd