00001 ------------------------------------------------------------------------------ 00002 -- This file is a part of the LPP VHDL IP LIBRARY 00003 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS 00004 -- 00005 -- This program is free software; you can redistribute it and/or modify 00006 -- it under the terms of the GNU General Public License as published by 00007 -- the Free Software Foundation; either version 3 of the License, or 00008 -- (at your option) any later version. 00009 -- 00010 -- This program is distributed in the hope that it will be useful, 00011 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 00012 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00013 -- GNU General Public License for more details. 00014 -- 00015 -- You should have received a copy of the GNU General Public License 00016 -- along with this program; if not, write to the Free Software 00017 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 00018 ------------------------------------------------------------------------------ 00019 -- Author : Martin Morlot 00020 -- Mail : martin.morlot@lpp.polytechnique.fr 00021 ------------------------------------------------------------------------------ 00022 library ieee; 00023 use ieee.std_logic_1164.all; 00024 library grlib; 00025 use grlib.amba.all; 00026 use std.textio.all; 00027 library lpp; 00028 use lpp.lpp_amba.all; 00029 00031 00032 package lpp_cna is 00033 00034 component APB_CNA is 00035 generic ( 00036 pindex : integer := 0; 00037 paddr : integer := 0; 00038 pmask : integer := 16#fff#; 00039 pirq : integer := 0; 00040 abits : integer := 8); 00041 port ( 00042 clk : in std_logic; 00043 rst : in std_logic; 00044 apbi : in apb_slv_in_type; 00045 apbo : out apb_slv_out_type; 00046 SYNC : out std_logic; 00047 SCLK : out std_logic; 00048 DATA : out std_logic 00049 ); 00050 end component; 00051 00052 00053 component CNA_TabloC is 00054 port( 00055 clock : in std_logic; 00056 rst : in std_logic; 00057 flag_nw : in std_logic; 00058 bp : in std_logic; 00059 Data_C : in std_logic_vector(15 downto 0); 00060 SYNC : out std_logic; 00061 SCLK : out std_logic; 00062 Rz : out std_logic; 00063 flag_sd : out std_logic; 00064 Data : out std_logic 00065 ); 00066 end component; 00067 00068 00069 component Systeme_Clock is 00070 generic(N :integer := 695); 00071 port( 00072 clk, raz : in std_logic ; 00073 clock : out std_logic); 00074 end component; 00075 00076 00077 component Gene_SYNC is 00078 port( 00079 clk,raz : in std_logic; 00080 send : in std_logic; 00081 Sysclk : in std_logic; 00082 OKAI_send : out std_logic; 00083 SYNC : out std_logic); 00084 end component; 00085 00086 00087 component Serialize is 00088 port( 00089 clk,raz : in std_logic; 00090 sclk : in std_logic; 00091 vectin : in std_logic_vector(15 downto 0); 00092 send : in std_logic; 00093 sended : out std_logic; 00094 Data : out std_logic); 00095 end component; 00096 00097 end;
© Copyright 2011 LPP-CNRS | Design by Alexis Jeandet