ar_TestbenshALU Member List

This is the complete list of members for ar_TestbenshALU, including all inherited members.

ADD	ar_TestbenshALU	[Constant]
ALU.ADD	MAC_CONTROLER	[Port]
add	ar_MAC	[Signal]
Adder.add	Adder	[Port]
add_D	ar_MAC	[Signal]
adder_inst	ar_MAC	[Component Instantiation]
ADDERinA	ar_MAC	[Signal]
ADDERinB	ar_MAC	[Signal]
ADDERout	ar_MAC	[Signal]
addREG	ar_MAC	[Component Instantiation]
ALU1	ar_TestbenshALU	[Component Instantiation]
Arith_en	ALU	[Generic]
clk	ar_TestbenshALU	[Signal]
ALU.ALU::ar_ALU.MAC::ar_MAC.Multiplier.clk	Multiplier	[Port]
ALU.ALU::ar_ALU.MAC::ar_MAC.Adder.clk	Adder	[Port]
ALU.ALU::ar_ALU.MAC::ar_MAC.MAC_REG.clk	MAC_REG	[Port]
clr	Adder	[Port]
clr_mac	ar_TestbenshALU	[Constant]
clr_MAC	ar_ALU	[Signal]
clr_MAC_D	ar_MAC	[Signal]
clr_MAC_D_D	ar_MAC	[Signal]
clr_MACREG1	ar_MAC	[Component Instantiation]
clr_MACREG2	ar_MAC	[Component Instantiation]
ctrl	ar_TestbenshALU	[Signal]
ALU.ALU::ar_ALU.ctrl	MAC_CONTROLER	[Port]
D	MAC_REG	[Port]
general_purpose	ALU	[Package]
ALU::ar_ALU.MAC::ar_MAC.MAC_CONTROLER.general_purpose	MAC_CONTROLER	[Package]
ALU::ar_ALU.MAC::ar_MAC.Multiplier.general_purpose	Multiplier	[Package]
ALU::ar_ALU.MAC::ar_MAC.Adder.general_purpose	Adder	[Package]
ALU::ar_ALU.MAC::ar_MAC.MAC_REG.general_purpose	MAC_REG	[Package]
ALU::ar_ALU.MAC::ar_MAC.MAC_MUX.general_purpose	MAC_MUX	[Package]
IDLE	ar_TestbenshALU	[Constant]
IEEE	ALU	[Library]
ALU::ar_ALU.MAC::ar_MAC.MAC_CONTROLER.IEEE	MAC_CONTROLER	[Library]
ALU::ar_ALU.MAC::ar_MAC.Multiplier.IEEE	Multiplier	[Library]
ALU::ar_ALU.MAC::ar_MAC.Adder.IEEE	Adder	[Library]
ALU::ar_ALU.MAC::ar_MAC.MAC_REG.IEEE	MAC_REG	[Library]
ALU::ar_ALU.MAC::ar_MAC.MAC_MUX.IEEE	MAC_MUX	[Library]
INA1	MAC_MUX	[Port]
INA2	MAC_MUX	[Port]
INB1	MAC_MUX	[Port]
INB2	MAC_MUX	[Port]
Input_SZ	MAC_MUX2	[Generic]
Input_SZ_1	ALU	[Generic]
Input_SZ_2	ALU	[Generic]
Input_SZ_A	MAC	[Generic]
MAC::ar_MAC.Multiplier.Input_SZ_A	Multiplier	[Generic]
MAC::ar_MAC.Adder.Input_SZ_A	Adder	[Generic]
MAC::ar_MAC.MAC_MUX.Input_SZ_A	MAC_MUX	[Generic]
Input_SZ_B	MAC	[Generic]
MAC::ar_MAC.Multiplier.Input_SZ_B	Multiplier	[Generic]
MAC::ar_MAC.Adder.Input_SZ_B	Adder	[Generic]
MAC::ar_MAC.MAC_MUX.Input_SZ_B	MAC_MUX	[Generic]
Logic_en	ALU	[Generic]
lpp	ALU	[Library]
ALU::ar_ALU.MAC::ar_MAC.MAC_CONTROLER.lpp	MAC_CONTROLER	[Library]
ALU::ar_ALU.MAC::ar_MAC.Multiplier.lpp	Multiplier	[Library]
ALU::ar_ALU.MAC::ar_MAC.Adder.lpp	Adder	[Library]
ALU::ar_ALU.MAC::ar_MAC.MAC_REG.lpp	MAC_REG	[Library]
ALU::ar_ALU.MAC::ar_MAC.MAC_MUX.lpp	MAC_MUX	[Library]
MAC	ar_TestbenshALU	[Constant]
MAC_CONTROLER1	ar_MAC	[Component Instantiation]
MAC_MUL_ADD	MAC	[Port]
MAC_MUX2_inst	ar_MAC	[Component Instantiation]
MACinst	ar_ALU	[Component Instantiation]
MACMUX2_sel	MAC_CONTROLER	[Port]
MACMUX2sel	ar_MAC	[Signal]
MACMUX2sel_D	ar_MAC	[Signal]
MACMUX2sel_D_D	ar_MAC	[Signal]
MACMUX2selREG	ar_MAC	[Component Instantiation]
MACMUX2selREG2	ar_MAC	[Component Instantiation]
MACMUX_inst	ar_MAC	[Component Instantiation]
MACMUX_sel	MAC_CONTROLER	[Port]
MACMUXsel	ar_MAC	[Signal]
MACMUXsel_D	ar_MAC	[Signal]
MACMUXselREG	ar_MAC	[Component Instantiation]
mult	ar_MAC	[Signal]
Multiplier.mult	Multiplier	[Port]
MULT	ar_TestbenshALU	[Constant]
ALU.MULT	MAC_CONTROLER	[Port]
Multiplieri_nst	ar_MAC	[Component Instantiation]
MULTout	ar_MAC	[Signal]
MULTout_D	ar_MAC	[Signal]
MULToutREG	ar_MAC	[Component Instantiation]
numeric_std	ALU	[Package]
ALU::ar_ALU.MAC::ar_MAC.MAC_CONTROLER.numeric_std	MAC_CONTROLER	[Package]
ALU::ar_ALU.MAC::ar_MAC.Multiplier.numeric_std	Multiplier	[Package]
ALU::ar_ALU.MAC::ar_MAC.Adder.numeric_std	Adder	[Package]
ALU::ar_ALU.MAC::ar_MAC.MAC_REG.numeric_std	MAC_REG	[Package]
ALU::ar_ALU.MAC::ar_MAC.MAC_MUX.numeric_std	MAC_MUX	[Package]
OP1	ALU	[Port]
ALU::ar_ALU.MAC::ar_MAC.Multiplier.OP1	Multiplier	[Port]
ALU::ar_ALU.MAC::ar_MAC.Adder.OP1	Adder	[Port]
OP1_D	ar_MAC	[Signal]
OP1_D_Resz	ar_MAC	[Signal]
OP1REG	ar_MAC	[Component Instantiation]
OP1sz	ar_TestbenshALU	[Constant]
OP2	ALU	[Port]
ALU::ar_ALU.MAC::ar_MAC.Multiplier.OP2	Multiplier	[Port]
ALU::ar_ALU.MAC::ar_MAC.Adder.OP2	Adder	[Port]
OP2_D	ar_MAC	[Signal]
OP2_D_Resz	ar_MAC	[Signal]
OP2REG	ar_MAC	[Component Instantiation]
OP2sz	ar_TestbenshALU	[Constant]
Operand1	ar_TestbenshALU	[Signal]
Operand2	ar_TestbenshALU	[Signal]
OUTA	MAC_MUX	[Port]
OUTB	MAC_MUX	[Port]
PROCESS_15(clk, reset)	ar_Adder	[Process]
PROCESS_18(clk, reset)	ar_MAC_REG	[Process]
PROCESS_19(clk, reset)	ar_Multiplier	[Process]
PROCESS_22()	ar_TestbenshALU	[Process]
Q	MAC_REG	[Port]
Multiplier.REG	ar_Multiplier	[Signal]
Adder.REG	ar_Adder	[Signal]
RES	ALU	[Port]
ALU::ar_ALU.MAC::ar_MAC.Multiplier.RES	Multiplier	[Port]
ALU::ar_ALU.MAC::ar_MAC.Adder.RES	Adder	[Port]
RES1	MAC_MUX2	[Port]
RES2	MAC_MUX2	[Port]
RESADD	ar_Adder	[Signal]
reset	ar_TestbenshALU	[Signal]
ALU.ALU::ar_ALU.MAC::ar_MAC.Multiplier.reset	Multiplier	[Port]
ALU.ALU::ar_ALU.MAC::ar_MAC.Adder.reset	Adder	[Port]
ALU.ALU::ar_ALU.MAC::ar_MAC.MAC_REG.reset	MAC_REG	[Port]
RESMULT	ar_Multiplier	[Signal]
Resultat	ar_TestbenshALU	[Signal]
MAC_MUX.sel	MAC_MUX	[Port]
MAC_MUX2.sel	MAC_MUX2	[Port]
size	MAC_REG	[Generic]
std_logic_1164	ALU	[Package]
ALU::ar_ALU.MAC::ar_MAC.MAC_CONTROLER.std_logic_1164	MAC_CONTROLER	[Package]
ALU::ar_ALU.MAC::ar_MAC.Multiplier.std_logic_1164	Multiplier	[Package]
ALU::ar_ALU.MAC::ar_MAC.Adder.std_logic_1164	Adder	[Package]
ALU::ar_ALU.MAC::ar_MAC.MAC_REG.std_logic_1164	MAC_REG	[Package]
ALU::ar_ALU.MAC::ar_MAC.MAC_MUX.std_logic_1164	MAC_MUX	[Package]