lib-lpp: Main Page

This is the complete list of members for lpp_ad_conv, including all inherited members.

CNV	lpp_ad_conv	`[Record]`
SCK	lpp_ad_conv	`[Record]`
SDI	lpp_ad_conv	`[Record]`
CTRL_Reg	ar_lpp_apb_ad_conv	`[Record]`
sample	ar_lpp_apb_ad_conv	`[Record]`
abits	lpp_apb_ad_conv	`[Generic]`
AD7688	lpp_ad_conv	`[Constant]`
lpp_apb_ad_conv.AD7688	ar_lpp_apb_ad_conv	`[Component Instantiation]`
AD7688_drvr	lpp_ad_conv	`[Component]`
AD7688_in	lpp_ad_conv	`[Type]`
AD7688_in_element	lpp_ad_conv	`[Record]`
AD7688_out	lpp_ad_conv	`[Record]`
AD7688_spi_if	lpp_ad_conv	`[Component]`
AD7688_drvr.AD_in	AD7688_drvr	`[Port]`
lpp_apb_ad_conv.AD_in	lpp_apb_ad_conv	`[Port]`
lpp_apb_ad_conv.lpp_apb_ad_conv::ar_lpp_apb_ad_conv.AD7688_drvr.AD_in	AD7688_drvr	`[Port]`
lpp_apb_ad_conv.lpp_apb_ad_conv::ar_lpp_apb_ad_conv.ADS7886_drvr.AD_in	ADS7886_drvr	`[Port]`
ADS7886_drvr.AD_in	ADS7886_drvr	`[Port]`
AD7688_drvr.AD_out	AD7688_drvr	`[Port]`
lpp_apb_ad_conv.AD_out	lpp_apb_ad_conv	`[Port]`
lpp_apb_ad_conv.lpp_apb_ad_conv::ar_lpp_apb_ad_conv.AD7688_drvr.AD_out	AD7688_drvr	`[Port]`
lpp_apb_ad_conv.lpp_apb_ad_conv::ar_lpp_apb_ad_conv.ADS7886_drvr.AD_out	ADS7886_drvr	`[Port]`
ADS7886_drvr.AD_out	ADS7886_drvr	`[Port]`
ADCref	lpp_apb_ad_conv	`[Generic]`
ADS7886	lpp_ad_conv	`[Constant]`
lpp_apb_ad_conv.ADS7886	ar_lpp_apb_ad_conv	`[Component Instantiation]`
ADS7886_drvr	lpp_ad_conv	`[Component]`
amba	lpp_ad_conv	`[Package]`
lpp_apb_ad_conv.amba	lpp_apb_ad_conv	`[Package]`
apb_devices_list	lpp_apb_ad_conv	`[Package]`
apbi	lpp_apb_ad_conv	`[Port]`
apbo	lpp_apb_ad_conv	`[Port]`
AD7688_drvr.ChanelCount	AD7688_drvr	`[Generic]`
lpp_apb_ad_conv.ChanelCount	lpp_apb_ad_conv	`[Generic]`
lpp_apb_ad_conv.lpp_apb_ad_conv::ar_lpp_apb_ad_conv.AD7688_drvr.ChanelCount	AD7688_drvr	`[Generic]`
lpp_apb_ad_conv.lpp_apb_ad_conv::ar_lpp_apb_ad_conv.ADS7886_drvr.ChanelCount	ADS7886_drvr	`[Generic]`
ADS7886_drvr.ChanelCount	ADS7886_drvr	`[Generic]`
AD7688_drvr.clk	AD7688_drvr	`[Port]`
AD7688_drvr.AD7688_drvr::ar_AD7688_drvr.Clk_divider.clk	Clk_divider	`[Port]`
lpp_apb_ad_conv.clk	lpp_apb_ad_conv	`[Port]`
lpp_apb_ad_conv.lpp_apb_ad_conv::ar_lpp_apb_ad_conv.AD7688_drvr.clk	AD7688_drvr	`[Port]`
lpp_apb_ad_conv.lpp_apb_ad_conv::ar_lpp_apb_ad_conv.ADS7886_drvr.clk	ADS7886_drvr	`[Port]`
ADS7886_drvr.clk	ADS7886_drvr	`[Port]`
AD7688_drvr.clk_divided	Clk_divider	`[Port]`
lpp_apb_ad_conv.AD7688_drvr.clk_divided	Clk_divider	`[Port]`
lpp_apb_ad_conv.ADS7886_drvr.clk_divided	Clk_divider	`[Port]`
lpp_apb_ad_conv.Clk_divider.clk_divided	Clk_divider	`[Port]`
ADS7886_drvr.clk_divided	Clk_divider	`[Port]`
AD7688_drvr.clk_int	ar_AD7688_drvr	`[Signal]`
AD7688_drvr.Clk_divider.clk_int	ar_Clk_divider	`[Signal]`
lpp_apb_ad_conv.AD7688_drvr.clk_int	ar_AD7688_drvr	`[Signal]`
lpp_apb_ad_conv.AD7688_drvr.Clk_divider.clk_int	ar_Clk_divider	`[Signal]`
lpp_apb_ad_conv.ADS7886_drvr.clk_int	ar_ADS7886_drvr	`[Signal]`
lpp_apb_ad_conv.ADS7886_drvr.Clk_divider.clk_int	ar_Clk_divider	`[Signal]`
lpp_apb_ad_conv.Clk_divider.clk_int	ar_Clk_divider	`[Signal]`
ADS7886_drvr.clk_int	ar_ADS7886_drvr	`[Signal]`
ADS7886_drvr.Clk_divider.clk_int	ar_Clk_divider	`[Signal]`
AD7688_drvr.clk_TRIGER	ar_Clk_divider	`[Constant]`
lpp_apb_ad_conv.AD7688_drvr.clk_TRIGER	ar_Clk_divider	`[Constant]`
lpp_apb_ad_conv.ADS7886_drvr.clk_TRIGER	ar_Clk_divider	`[Constant]`
lpp_apb_ad_conv.Clk_divider.clk_TRIGER	ar_Clk_divider	`[Constant]`
ADS7886_drvr.clk_TRIGER	ar_Clk_divider	`[Constant]`
AD7688_drvr.clkdivider	ar_AD7688_drvr	`[Component Instantiation]`
lpp_apb_ad_conv.clkdivider	ar_lpp_apb_ad_conv	`[Component Instantiation]`
lpp_apb_ad_conv.AD7688_drvr.clkdivider	ar_AD7688_drvr	`[Component Instantiation]`
lpp_apb_ad_conv.ADS7886_drvr.clkdivider	ar_ADS7886_drvr	`[Component Instantiation]`
ADS7886_drvr.clkdivider	ar_ADS7886_drvr	`[Component Instantiation]`
AD7688_drvr.clkkHz	AD7688_drvr	`[Generic]`
lpp_apb_ad_conv.clkkHz	lpp_apb_ad_conv	`[Generic]`
lpp_apb_ad_conv.lpp_apb_ad_conv::ar_lpp_apb_ad_conv.AD7688_drvr.clkkHz	AD7688_drvr	`[Generic]`
lpp_apb_ad_conv.lpp_apb_ad_conv::ar_lpp_apb_ad_conv.ADS7886_drvr.clkkHz	ADS7886_drvr	`[Generic]`
ADS7886_drvr.clkkHz	ADS7886_drvr	`[Generic]`
AD7688_drvr.cnv	AD7688_spi_if	`[Port]`
AD7688_spi_if.cnv	AD7688_spi_if	`[Port]`
lpp_apb_ad_conv.AD7688_drvr.cnv	AD7688_spi_if	`[Port]`
lpp_apb_ad_conv.ADS7886_drvr.cnv	AD7688_spi_if	`[Port]`
ADS7886_drvr.cnv	AD7688_spi_if	`[Port]`
AD7688_drvr.cnv_int	ar_AD7688_drvr	`[Signal]`
lpp_apb_ad_conv.AD7688_drvr.cnv_int	ar_AD7688_drvr	`[Signal]`
lpp_apb_ad_conv.ADS7886_drvr.cnv_int	ar_ADS7886_drvr	`[Signal]`
ADS7886_drvr.cnv_int	ar_ADS7886_drvr	`[Signal]`
AD7688_drvr.cnv_reg	ar_AD7688_spi_if	`[Signal]`
AD7688_spi_if.cnv_reg	ar_AD7688_spi_if	`[Signal]`
lpp_apb_ad_conv.AD7688_drvr.cnv_reg	ar_AD7688_spi_if	`[Signal]`
lpp_apb_ad_conv.ADS7886_drvr.cnv_reg	ar_AD7688_spi_if	`[Signal]`
ADS7886_drvr.cnv_reg	ar_AD7688_spi_if	`[Signal]`
AD7688_drvr.convTrigger	ar_AD7688_drvr	`[Constant]`
lpp_apb_ad_conv.AD7688_drvr.convTrigger	ar_AD7688_drvr	`[Constant]`
lpp_apb_ad_conv.ADS7886_drvr.convTrigger	ar_ADS7886_drvr	`[Constant]`
ADS7886_drvr.convTrigger	ar_ADS7886_drvr	`[Constant]`
AD7688_drvr.cpt1	ar_Clk_divider	`[Signal]`
lpp_apb_ad_conv.AD7688_drvr.cpt1	ar_Clk_divider	`[Signal]`
lpp_apb_ad_conv.ADS7886_drvr.cpt1	ar_Clk_divider	`[Signal]`
lpp_apb_ad_conv.Clk_divider.cpt1	ar_Clk_divider	`[Signal]`
ADS7886_drvr.cpt1	ar_Clk_divider	`[Signal]`
AD7688_drvr.DataReady	AD7688_drvr	`[Port]`
lpp_apb_ad_conv.DataReady	ar_lpp_apb_ad_conv	`[Signal]`
lpp_apb_ad_conv.AD7688_drvr.DataReady	AD7688_drvr	`[Port]`
lpp_apb_ad_conv.ADS7886_drvr.DataReady	ADS7886_drvr	`[Port]`
ADS7886_drvr.DataReady	ADS7886_drvr	`[Port]`
devices	lpp_ad_conv	`[Package]`
lpp_apb_ad_conv.devices	lpp_apb_ad_conv	`[Package]`
AD7688_drvr.general_purpose	AD7688_drvr	`[Package]`
lpp_apb_ad_conv.general_purpose	lpp_apb_ad_conv	`[Package]`
lpp_apb_ad_conv.lpp_apb_ad_conv::ar_lpp_apb_ad_conv.AD7688_drvr.general_purpose	AD7688_drvr	`[Package]`
lpp_apb_ad_conv.lpp_apb_ad_conv::ar_lpp_apb_ad_conv.ADS7886_drvr.general_purpose	ADS7886_drvr	`[Package]`
ADS7886_drvr.general_purpose	ADS7886_drvr	`[Package]`
grlib	lpp_ad_conv	`[Library]`
lpp_apb_ad_conv.grlib	lpp_apb_ad_conv	`[Library]`
AD7688_drvr.i	ar_AD7688_drvr	`[Signal]`
lpp_apb_ad_conv.AD7688_drvr.i	ar_AD7688_drvr	`[Signal]`
lpp_apb_ad_conv.ADS7886_drvr.i	ar_ADS7886_drvr	`[Signal]`
ADS7886_drvr.i	ar_ADS7886_drvr	`[Signal]`
IEEE	lpp_ad_conv	`[Library]`
AD7688_drvr.IEEE	AD7688_drvr	`[Library]`
AD7688_drvr.AD7688_drvr::ar_AD7688_drvr.Clk_divider.IEEE	Clk_divider	`[Library]`
lpp_apb_ad_conv.IEEE	lpp_apb_ad_conv	`[Library]`
lpp_apb_ad_conv.lpp_apb_ad_conv::ar_lpp_apb_ad_conv.AD7688_drvr.IEEE	AD7688_drvr	`[Library]`
AD7688_drvr.lpp	AD7688_drvr	`[Library]`
lpp_apb_ad_conv.lpp	lpp_apb_ad_conv	`[Library]`
lpp_apb_ad_conv.lpp_apb_ad_conv::ar_lpp_apb_ad_conv.AD7688_drvr.lpp	AD7688_drvr	`[Library]`
lpp_apb_ad_conv.lpp_apb_ad_conv::ar_lpp_apb_ad_conv.ADS7886_drvr.lpp	ADS7886_drvr	`[Library]`
ADS7886_drvr.lpp	ADS7886_drvr	`[Library]`
AD7688_drvr.lpp_ad_conv	AD7688_drvr	`[Package]`
lpp_apb_ad_conv.lpp_ad_conv	lpp_apb_ad_conv	`[Package]`
lpp_apb_ad_conv.lpp_apb_ad_conv::ar_lpp_apb_ad_conv.AD7688_drvr.lpp_ad_conv	AD7688_drvr	`[Package]`
lpp_apb_ad_conv.lpp_apb_ad_conv::ar_lpp_apb_ad_conv.ADS7886_drvr.lpp_ad_conv	ADS7886_drvr	`[Package]`
ADS7886_drvr.lpp_ad_conv	ADS7886_drvr	`[Package]`
lpp_amba	lpp_apb_ad_conv	`[Package]`
lpp_apb_ad_conv	lpp_ad_conv	`[Component]`
lpp_apb_ad_conv_Reg	ar_lpp_apb_ad_conv	`[Record]`
numeric_std	lpp_apb_ad_conv	`[Package]`
AD7688_drvr.OSC_freqHz	Clk_divider	`[Generic]`
lpp_apb_ad_conv.AD7688_drvr.OSC_freqHz	Clk_divider	`[Generic]`
lpp_apb_ad_conv.ADS7886_drvr.OSC_freqHz	Clk_divider	`[Generic]`
lpp_apb_ad_conv.Clk_divider.OSC_freqHz	Clk_divider	`[Generic]`
ADS7886_drvr.OSC_freqHz	Clk_divider	`[Generic]`
paddr	lpp_apb_ad_conv	`[Generic]`
pconfig	ar_lpp_apb_ad_conv	`[Constant]`
pindex	lpp_apb_ad_conv	`[Generic]`
pirq	lpp_apb_ad_conv	`[Generic]`
pmask	lpp_apb_ad_conv	`[Generic]`
AD7688_drvr.PROCESS_17(reset, clk)	ar_Clk_divider	`[Process]`
lpp_apb_ad_conv.AD7688_drvr.PROCESS_17(reset, clk)	ar_Clk_divider	`[Process]`
lpp_apb_ad_conv.ADS7886_drvr.PROCESS_17(reset, clk)	ar_Clk_divider	`[Process]`
lpp_apb_ad_conv.Clk_divider.PROCESS_17(reset, clk)	ar_Clk_divider	`[Process]`
ADS7886_drvr.PROCESS_17(reset, clk)	ar_Clk_divider	`[Process]`
AD7688_drvr.PROCESS_23(clk, reset)	ar_AD7688_spi_if	`[Process]`
AD7688_spi_if.PROCESS_23(clk, reset)	ar_AD7688_spi_if	`[Process]`
lpp_apb_ad_conv.AD7688_drvr.PROCESS_23(clk, reset)	ar_AD7688_spi_if	`[Process]`
lpp_apb_ad_conv.ADS7886_drvr.PROCESS_23(clk, reset)	ar_AD7688_spi_if	`[Process]`
ADS7886_drvr.PROCESS_23(clk, reset)	ar_AD7688_spi_if	`[Process]`
PROCESS_24(reset, clk)	ar_lpp_apb_ad_conv	`[Process]`
r	ar_lpp_apb_ad_conv	`[Signal]`
Rdata	ar_lpp_apb_ad_conv	`[Signal]`
AD7688_drvr.reset	AD7688_drvr	`[Port]`
AD7688_drvr.AD7688_drvr::ar_AD7688_drvr.Clk_divider.reset	Clk_divider	`[Port]`
lpp_apb_ad_conv.reset	lpp_apb_ad_conv	`[Port]`
lpp_apb_ad_conv.lpp_apb_ad_conv::ar_lpp_apb_ad_conv.AD7688_drvr.reset	AD7688_drvr	`[Port]`
lpp_apb_ad_conv.lpp_apb_ad_conv::ar_lpp_apb_ad_conv.ADS7886_drvr.reset	ADS7886_drvr	`[Port]`
ADS7886_drvr.reset	ADS7886_drvr	`[Port]`
REVISION	ar_lpp_apb_ad_conv	`[Constant]`
Samples_out	lpp_ad_conv	`[Type]`
AD7688_drvr.sckgen(clk, reset)	ar_AD7688_drvr	`[Process]`
lpp_apb_ad_conv.AD7688_drvr.sckgen(clk, reset)	ar_AD7688_drvr	`[Process]`
lpp_apb_ad_conv.ADS7886_drvr.sckgen(clk, reset)	ar_ADS7886_drvr	`[Process]`
ADS7886_drvr.sckgen(clk, reset)	ar_ADS7886_drvr	`[Process]`
AD7688_drvr.sdi	AD7688_spi_if	`[Port]`
AD7688_spi_if.sdi	AD7688_spi_if	`[Port]`
lpp_apb_ad_conv.AD7688_drvr.sdi	AD7688_spi_if	`[Port]`
lpp_apb_ad_conv.ADS7886_drvr.sdi	AD7688_spi_if	`[Port]`
ADS7886_drvr.sdi	AD7688_spi_if	`[Port]`
AD7688_drvr.shift_reg	ar_AD7688_spi_if	`[Signal]`
AD7688_spi_if.shift_reg	ar_AD7688_spi_if	`[Signal]`
lpp_apb_ad_conv.AD7688_drvr.shift_reg	ar_AD7688_spi_if	`[Signal]`
lpp_apb_ad_conv.ADS7886_drvr.shift_reg	ar_AD7688_spi_if	`[Signal]`
ADS7886_drvr.shift_reg	ar_AD7688_spi_if	`[Signal]`
smpClkHz	lpp_apb_ad_conv	`[Generic]`
AD7688_drvr.smplClk	AD7688_drvr	`[Port]`
lpp_apb_ad_conv.smplClk	ar_lpp_apb_ad_conv	`[Signal]`
lpp_apb_ad_conv.AD7688_drvr.smplClk	AD7688_drvr	`[Port]`
lpp_apb_ad_conv.ADS7886_drvr.smplClk	ADS7886_drvr	`[Port]`
ADS7886_drvr.smplClk	ADS7886_drvr	`[Port]`
AD7688_drvr.smplClk_reg	ar_AD7688_drvr	`[Signal]`
lpp_apb_ad_conv.AD7688_drvr.smplClk_reg	ar_AD7688_drvr	`[Signal]`
lpp_apb_ad_conv.ADS7886_drvr.smplClk_reg	ar_ADS7886_drvr	`[Signal]`
ADS7886_drvr.smplClk_reg	ar_ADS7886_drvr	`[Signal]`
AD7688_drvr.smpout	AD7688_drvr	`[Port]`
lpp_apb_ad_conv.smpout	ar_lpp_apb_ad_conv	`[Signal]`
lpp_apb_ad_conv.AD7688_drvr.smpout	AD7688_drvr	`[Port]`
lpp_apb_ad_conv.ADS7886_drvr.smpout	ADS7886_drvr	`[Port]`
ADS7886_drvr.smpout	ADS7886_drvr	`[Port]`
lpp_apb_ad_conv.smpout_int	ar_ADS7886_drvr	`[Signal]`
ADS7886_drvr.smpout_int	ar_ADS7886_drvr	`[Signal]`
AD7688_drvr.spidrvr	ar_AD7688_drvr	`[Component Instantiation]`
lpp_apb_ad_conv.AD7688_drvr.spidrvr	ar_AD7688_drvr	`[Component Instantiation]`
lpp_apb_ad_conv.ADS7886_drvr.spidrvr	ar_ADS7886_drvr	`[Component Instantiation]`
ADS7886_drvr.spidrvr	ar_ADS7886_drvr	`[Component Instantiation]`
STD_LOGIC_1164	lpp_ad_conv	`[Package]`
AD7688_drvr.STD_LOGIC_1164	AD7688_drvr	`[Package]`
AD7688_drvr.AD7688_drvr::ar_AD7688_drvr.Clk_divider.STD_LOGIC_1164	Clk_divider	`[Package]`
lpp_apb_ad_conv.STD_LOGIC_1164	lpp_apb_ad_conv	`[Package]`
lpp_apb_ad_conv.lpp_apb_ad_conv::ar_lpp_apb_ad_conv.AD7688_drvr.STD_LOGIC_1164	AD7688_drvr	`[Package]`
stdlib	lpp_ad_conv	`[Package]`
lpp_apb_ad_conv.stdlib	lpp_apb_ad_conv	`[Package]`
AD7688_drvr.TargetFreq_Hz	Clk_divider	`[Generic]`
lpp_apb_ad_conv.AD7688_drvr.TargetFreq_Hz	Clk_divider	`[Generic]`
lpp_apb_ad_conv.ADS7886_drvr.TargetFreq_Hz	Clk_divider	`[Generic]`
lpp_apb_ad_conv.Clk_divider.TargetFreq_Hz	Clk_divider	`[Generic]`
ADS7886_drvr.TargetFreq_Hz	Clk_divider	`[Generic]`

Free VHDL library

lpp_ad_conv Member List