ar_MAC Architecture Reference

Inherits MAC_CONTROLER, Multiplier, Adder, MAC_REG, MAC_MUX, and MAC_MUX2.

Inherited by MAC.

List of all members.

Signals
mult	std_logic
add	std_logic
MULTout	std_logic_vector ( Input_SZ_A +Input_SZ_B -1 downto 0 )
ADDERinA	std_logic_vector ( Input_SZ_A +Input_SZ_B -1 downto 0 )
ADDERinB	std_logic_vector ( Input_SZ_A +Input_SZ_B -1 downto 0 )
ADDERout	std_logic_vector ( Input_SZ_A +Input_SZ_B -1 downto 0 )
MACMUXsel	std_logic
OP1_D_Resz	std_logic_vector ( Input_SZ_A +Input_SZ_B -1 downto 0 )
OP2_D_Resz	std_logic_vector ( Input_SZ_A +Input_SZ_B -1 downto 0 )
MACMUX2sel	std_logic
add_D	std_logic
OP1_D	std_logic_vector ( Input_SZ_A -1 downto 0 )
OP2_D	std_logic_vector ( Input_SZ_B -1 downto 0 )
MULTout_D	std_logic_vector ( Input_SZ_A +Input_SZ_B -1 downto 0 )
MACMUXsel_D	std_logic
MACMUX2sel_D	std_logic
MACMUX2sel_D_D	std_logic
clr_MAC_D	std_logic
clr_MAC_D_D	std_logic
Component Instantiations
MAC_CONTROLER1	MAC_CONTROLER <Entity MAC_CONTROLER>
Multiplieri_nst	Multiplier <Entity Multiplier>
adder_inst	Adder <Entity Adder>
clr_MACREG1	MAC_REG <Entity MAC_REG>
clr_MACREG2	MAC_REG <Entity MAC_REG>
addREG	MAC_REG <Entity MAC_REG>
OP1REG	MAC_REG <Entity MAC_REG>
OP2REG	MAC_REG <Entity MAC_REG>
MULToutREG	MAC_REG <Entity MAC_REG>
MACMUXselREG	MAC_REG <Entity MAC_REG>
MACMUX2selREG	MAC_REG <Entity MAC_REG>
MACMUX2selREG2	MAC_REG <Entity MAC_REG>
MACMUX_inst	MAC_MUX <Entity MAC_MUX>
MAC_MUX2_inst	MAC_MUX2 <Entity MAC_MUX2>

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Detailed Description

Definition at line 55 of file MAC.vhd.

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Member Data Documentation

add std_logic [Signal]

Definition at line 61 of file MAC.vhd.

add_D std_logic [Signal]

Definition at line 77 of file MAC.vhd.

adder_inst Adder [Component Instantiation]

Definition at line 138 of file MAC.vhd.

ADDERinA std_logic_vector ( Input_SZ_A +Input_SZ_B -1 downto 0 ) [Signal]

Definition at line 64 of file MAC.vhd.

ADDERinB std_logic_vector ( Input_SZ_A +Input_SZ_B -1 downto 0 ) [Signal]

Definition at line 65 of file MAC.vhd.

ADDERout std_logic_vector ( Input_SZ_A +Input_SZ_B -1 downto 0 ) [Signal]

Definition at line 66 of file MAC.vhd.

addREG MAC_REG [Component Instantiation]

Definition at line 174 of file MAC.vhd.

clr_MAC_D std_logic [Signal]

Definition at line 84 of file MAC.vhd.

clr_MAC_D_D std_logic [Signal]

Definition at line 85 of file MAC.vhd.

clr_MACREG1 MAC_REG [Component Instantiation]

Definition at line 156 of file MAC.vhd.

clr_MACREG2 MAC_REG [Component Instantiation]

Definition at line 165 of file MAC.vhd.

MAC_CONTROLER1 MAC_CONTROLER [Component Instantiation]

Definition at line 99 of file MAC.vhd.

MAC_MUX2_inst MAC_MUX2 [Component Instantiation]

Definition at line 266 of file MAC.vhd.

MACMUX2sel std_logic [Signal]

Definition at line 75 of file MAC.vhd.

MACMUX2sel_D std_logic [Signal]

Definition at line 82 of file MAC.vhd.

MACMUX2sel_D_D std_logic [Signal]

Definition at line 83 of file MAC.vhd.

MACMUX2selREG MAC_REG [Component Instantiation]

Definition at line 222 of file MAC.vhd.

MACMUX2selREG2 MAC_REG [Component Instantiation]

Definition at line 231 of file MAC.vhd.

MACMUX_inst MAC_MUX [Component Instantiation]

Definition at line 243 of file MAC.vhd.

MACMUXsel std_logic [Signal]

Definition at line 69 of file MAC.vhd.

MACMUXsel_D std_logic [Signal]

Definition at line 81 of file MAC.vhd.

MACMUXselREG MAC_REG [Component Instantiation]

Definition at line 213 of file MAC.vhd.

mult std_logic [Signal]

Definition at line 61 of file MAC.vhd.

Multiplieri_nst Multiplier [Component Instantiation]

Definition at line 116 of file MAC.vhd.

MULTout std_logic_vector ( Input_SZ_A +Input_SZ_B -1 downto 0 ) [Signal]

Definition at line 62 of file MAC.vhd.

MULTout_D std_logic_vector ( Input_SZ_A +Input_SZ_B -1 downto 0 ) [Signal]

Definition at line 80 of file MAC.vhd.

MULToutREG MAC_REG [Component Instantiation]

Definition at line 203 of file MAC.vhd.

OP1_D std_logic_vector ( Input_SZ_A -1 downto 0 ) [Signal]

Definition at line 78 of file MAC.vhd.

OP1_D_Resz std_logic_vector ( Input_SZ_A +Input_SZ_B -1 downto 0 ) [Signal]

Definition at line 70 of file MAC.vhd.

OP1REG MAC_REG [Component Instantiation]

Definition at line 183 of file MAC.vhd.

OP2_D std_logic_vector ( Input_SZ_B -1 downto 0 ) [Signal]

Definition at line 79 of file MAC.vhd.

OP2_D_Resz std_logic_vector ( Input_SZ_A +Input_SZ_B -1 downto 0 ) [Signal]

Definition at line 71 of file MAC.vhd.

OP2REG MAC_REG [Component Instantiation]

Definition at line 193 of file MAC.vhd.

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The documentation for this class was generated from the following file:

• general_purpose/MAC.vhd