00001 ------------------------------------------------------------------------------ 00002 -- This file is a part of the LPP VHDL IP LIBRARY 00003 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS 00004 -- 00005 -- This program is free software; you can redistribute it and/or modify 00006 -- it under the terms of the GNU General Public License as published by 00007 -- the Free Software Foundation; either version 3 of the License, or 00008 -- (at your option) any later version. 00009 -- 00010 -- This program is distributed in the hope that it will be useful, 00011 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 00012 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00013 -- GNU General Public License for more details. 00014 -- 00015 -- You should have received a copy of the GNU General Public License 00016 -- along with this program; if not, write to the Free Software 00017 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 00018 ------------------------------------------------------------------------------ 00019 -- Author : Martin Morlot 00020 -- Mail : martin.morlot@lpp.polytechnique.fr 00021 ------------------------------------------------------------------------------ 00022 library ieee; 00023 use ieee.std_logic_1164.all; 00024 library grlib; 00025 use grlib.amba.all; 00026 use std.textio.all; 00027 library lpp; 00028 use lpp.lpp_amba.all; 00029 00031 00032 package lpp_memory is 00033 00034 --===========================================================| 00035 --=================== FIFO Complète =========================| 00036 --===========================================================| 00037 00038 component APB_FIFO is 00039 generic ( 00040 pindex : integer := 0; 00041 paddr : integer := 0; 00042 pmask : integer := 16#fff#; 00043 pirq : integer := 0; 00044 abits : integer := 8; 00045 Data_sz : integer := 16; 00046 Addr_sz : integer := 8; 00047 addr_max_int : integer := 256); 00048 port ( 00049 clk : in std_logic; 00050 rst : in std_logic; 00051 apbi : in apb_slv_in_type; 00052 apbo : out apb_slv_out_type 00053 ); 00054 end component; 00055 00056 00057 component ApbDriver is 00058 generic ( 00059 pindex : integer := 0; 00060 paddr : integer := 0; 00061 pmask : integer := 16#fff#; 00062 pirq : integer := 0; 00063 abits : integer := 8; 00064 LPP_DEVICE : integer; 00065 Data_sz : integer := 16; 00066 Addr_sz : integer := 8; 00067 addr_max_int : integer := 256); 00068 port ( 00069 clk : in std_logic; 00070 rst : in std_logic; 00071 ReadEnable : in std_logic; 00072 WriteEnable : in std_logic; 00073 FlagEmpty : in std_logic; 00074 FlagFull : in std_logic; 00075 DataIn : out std_logic_vector(Data_sz-1 downto 0); 00076 DataOut : in std_logic_vector(Data_sz-1 downto 0); 00077 AddrIn : in std_logic_vector(Addr_sz-1 downto 0); 00078 AddrOut : in std_logic_vector(Addr_sz-1 downto 0); 00079 apbi : in apb_slv_in_type; 00080 apbo : out apb_slv_out_type 00081 ); 00082 end component; 00083 00084 00085 component Top_FIFO is 00086 generic( 00087 Data_sz : integer := 16; 00088 Addr_sz : integer := 8; 00089 addr_max_int : integer := 256 00090 ); 00091 port( 00092 clk,raz : in std_logic; 00093 flag_RE : in std_logic; 00094 flag_WR : in std_logic; 00095 Data_in : in std_logic_vector(Data_sz-1 downto 0); 00096 Addr_RE : out std_logic_vector(addr_sz-1 downto 0); 00097 Addr_WR : out std_logic_vector(addr_sz-1 downto 0); 00098 full : out std_logic; 00099 empty : out std_logic; 00100 Data_out : out std_logic_vector(Data_sz-1 downto 0) 00101 ); 00102 end component; 00103 00104 00105 component Fifo_Read is 00106 generic( 00107 Addr_sz : integer := 8; 00108 addr_max_int : integer := 256); 00109 port( 00110 clk : in std_logic; 00111 raz : in std_logic; 00112 flag_RE : in std_logic; 00113 Waddr : in std_logic_vector(addr_sz-1 downto 0); 00114 empty : out std_logic; 00115 Raddr : out std_logic_vector(addr_sz-1 downto 0) 00116 ); 00117 end component; 00118 00119 00120 component Fifo_Write is 00121 generic( 00122 Addr_sz : integer := 8; 00123 addr_max_int : integer := 256); 00124 port( 00125 clk : in std_logic; 00126 raz : in std_logic; 00127 flag_WR : in std_logic; 00128 Raddr : in std_logic_vector(addr_sz-1 downto 0); 00129 full : out std_logic; 00130 Waddr : out std_logic_vector(addr_sz-1 downto 0) 00131 ); 00132 end component; 00133 00134 00135 component Link_Reg is 00136 generic(Data_sz : integer := 16); 00137 port( 00138 clk,raz : in std_logic; 00139 Data_one : in std_logic_vector(Data_sz-1 downto 0); 00140 Data_two : in std_logic_vector(Data_sz-1 downto 0); 00141 flag_RE : in std_logic; 00142 flag_WR : in std_logic; 00143 empty : in std_logic; 00144 Data_out : out std_logic_vector(Data_sz-1 downto 0) 00145 ); 00146 end component; 00147 00148 --===========================================================| 00149 --================= Demi FIFO Ecriture ======================| 00150 --===========================================================| 00151 00152 component APB_FifoWrite is 00153 generic ( 00154 pindex : integer := 0; 00155 paddr : integer := 0; 00156 pmask : integer := 16#fff#; 00157 pirq : integer := 0; 00158 abits : integer := 8; 00159 Data_sz : integer := 16; 00160 Addr_sz : integer := 8; 00161 addr_max_int : integer := 256); 00162 port ( 00163 clk : in std_logic; 00164 rst : in std_logic; 00165 apbi : in apb_slv_in_type; 00166 apbo : out apb_slv_out_type 00167 ); 00168 end component; 00169 00170 00171 component Top_FifoWrite is 00172 generic( 00173 Data_sz : integer := 16; 00174 Addr_sz : integer := 8; 00175 addr_max_int : integer := 256); 00176 port( 00177 clk : in std_logic; 00178 raz : in std_logic; 00179 flag_RE : in std_logic; 00180 flag_WR : in std_logic; 00181 Data_in : in std_logic_vector(Data_sz-1 downto 0); 00182 Raddr : in std_logic_vector(addr_sz-1 downto 0); 00183 full : out std_logic; 00184 empty : out std_logic; 00185 Waddr : out std_logic_vector(addr_sz-1 downto 0); 00186 Data_out : out std_logic_vector(Data_sz-1 downto 0) 00187 ); 00188 end component; 00189 00190 --===========================================================| 00191 --================== Demi FIFO Lecture ======================| 00192 --===========================================================| 00193 00194 component APB_FifoRead is 00195 generic ( 00196 pindex : integer := 0; 00197 paddr : integer := 0; 00198 pmask : integer := 16#fff#; 00199 pirq : integer := 0; 00200 abits : integer := 8; 00201 Data_sz : integer := 16; 00202 Addr_sz : integer := 8; 00203 addr_max_int : integer := 256); 00204 port ( 00205 clk : in std_logic; 00206 rst : in std_logic; 00207 apbi : in apb_slv_in_type; 00208 apbo : out apb_slv_out_type 00209 ); 00210 end component; 00211 00212 00213 component Top_FifoRead is 00214 generic( 00215 Data_sz : integer := 16; 00216 Addr_sz : integer := 8; 00217 addr_max_int : integer := 256); 00218 port( 00219 clk : in std_logic; 00220 raz : in std_logic; 00221 flag_RE : in std_logic; 00222 flag_WR : in std_logic; 00223 Data_in : in std_logic_vector(Data_sz-1 downto 0); 00224 Waddr : in std_logic_vector(addr_sz-1 downto 0); 00225 full : out std_logic; 00226 empty : out std_logic; 00227 Raddr : out std_logic_vector(addr_sz-1 downto 0); 00228 Data_out : out std_logic_vector(Data_sz-1 downto 0) 00229 ); 00230 end component; 00231 00232 end;
© Copyright 2011 LPP-CNRS | Design by Alexis Jeandet