APB_IIR_CEL Member List

This is the complete list of members for APB_IIR_CEL, including all inherited members.

regin	AR_APB_IIR_CEL	[Record]
regout	AR_APB_IIR_CEL	[Record]
numCoefs	AR_APB_IIR_CEL	[Record]
denCoefs	AR_APB_IIR_CEL	[Record]
numCoefs	ar_IIR_CEL_CTRLR	[Record]
denCoefs	ar_IIR_CEL_CTRLR	[Record]
abits	APB_IIR_CEL	[Generic]
add	ar_MAC	[Signal]
Adder.add	Adder	[Port]
ADD	MAC_CONTROLER	[Port]
add_D	ar_MAC	[Signal]
adder_inst	ar_MAC	[Component Instantiation]
ADDERinA	ar_MAC	[Signal]
ADDERinB	ar_MAC	[Signal]
ADDERout	ar_MAC	[Signal]
ADDRcntr_inst	ar_RAM_CTRLR2	[Component Instantiation]
addREG	ar_MAC	[Component Instantiation]
ADDRreg	ar_RAM_CTRLR2	[Component Instantiation]
ALU_Coef_in	ar_IIR_CEL_CTRLR	[Signal]
ALU_ctrl	ar_IIR_CEL_CTRLR	[Signal]
ALU_inst	ar_IIR_CEL_CTRLR	[Component Instantiation]
ALU_out	ar_IIR_CEL_CTRLR	[Signal]
ALU_sample_in	ar_IIR_CEL_CTRLR	[Signal]
amba	APB_IIR_CEL	[Package]
apb_devices_list	APB_IIR_CEL	[Package]
apbi	APB_IIR_CEL	[Port]
apbo	APB_IIR_CEL	[Port]
Arith_en	ALU	[Generic]
bootmsg	AR_APB_IIR_CEL	[Component Instantiation]
Cels_count	APB_IIR_CEL	[Generic]
ChanelsCount	APB_IIR_CEL	[Generic]
clk	APB_IIR_CEL	[Port]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.RAM_CTRLR2.clk	RAM_CTRLR2	[Port]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.RAM_CTRLR2.RAM_CTRLR2::ar_RAM_CTRLR2.ADDRcntr.clk	ADDRcntr	[Port]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.Multiplier.clk	Multiplier	[Port]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.Adder.clk	Adder	[Port]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.MAC_REG.clk	MAC_REG	[Port]
RAM_CTRLR2.clr	ADDRcntr	[Port]
ALU.clr	Adder	[Port]
clr_MAC	ar_ALU	[Signal]
clr_MAC_D	ar_MAC	[Signal]
clr_MAC_D_D	ar_MAC	[Signal]
clr_MACREG1	ar_MAC	[Component Instantiation]
clr_MACREG2	ar_MAC	[Component Instantiation]
Coef_SZ	APB_IIR_CEL	[Generic]
CoefCelT	AR_APB_IIR_CEL	[Type]
CoefCntPerCel	APB_IIR_CEL	[Generic]
coefs	IIR_CEL_FILTER	[Port]
CoefsReg	AR_APB_IIR_CEL	[Signal]
CoefsRegT	AR_APB_IIR_CEL	[Record]
CoefTblT	AR_APB_IIR_CEL	[Type]
count	ar_IIR_CEL_CTRLR	[Signal]
RAM_CTRLR2.count	RAM_CTRLR2	[Port]
RAM_CTRLR2.RAM_CTRLR2::ar_RAM_CTRLR2.count	ADDRcntr	[Port]
ctrl	ALU	[Port]
ALU::ar_ALU.ctrl	MAC_CONTROLER	[Port]
CTRLR	ar_IIR_CEL_FILTER	[Component Instantiation]
curentCel	ar_IIR_CEL_CTRLR	[Signal]
curentChan	ar_IIR_CEL_CTRLR	[Signal]
RAM_CTRLR2.D	REG	[Port]
ALU.D	MAC_REG	[Port]
devices	APB_IIR_CEL	[Package]
filter	AR_APB_IIR_CEL	[Component Instantiation]
filter_reset	AR_APB_IIR_CEL	[Signal]
FILTERcfg	RAM_CTRLR2	[Package]
FILTERreg	AR_APB_IIR_CEL	[Record]
fsmIIR_CEL_T	ar_IIR_CEL_CTRLR	[Type]
general_purpose	APB_IIR_CEL	[Package]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.RAM_CTRLR2.general_purpose	RAM_CTRLR2	[Package]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.RAM_CTRLR2.RAM_CTRLR2::ar_RAM_CTRLR2.ADDRcntr.general_purpose	ADDRcntr	[Package]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.RAM_CTRLR2.RAM_CTRLR2::ar_RAM_CTRLR2.MUX2.general_purpose	MUX2	[Package]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.MAC_CONTROLER.general_purpose	MAC_CONTROLER	[Package]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.Multiplier.general_purpose	Multiplier	[Package]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.Adder.general_purpose	Adder	[Package]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.MAC_REG.general_purpose	MAC_REG	[Package]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.MAC_MUX.general_purpose	MAC_MUX	[Package]
GO_0	ar_IIR_CEL_CTRLR	[Signal]
RAM_CTRLR2.GO_0	RAM_CTRLR2	[Port]
grlib	APB_IIR_CEL	[Library]
ieee	APB_IIR_CEL	[Library]
APB_IIR_CEL::AR_APB_IIR_CEL.RAM.ieee	RAM	[Library]
APB_IIR_CEL::AR_APB_IIR_CEL.RAM_CEL.ieee	RAM_CEL	[Library]
IEEE	IIR_CEL_FILTER	[Library]
IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.RAM_CTRLR2.IEEE	RAM_CTRLR2	[Library]
IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.RAM_CTRLR2.RAM_CTRLR2::ar_RAM_CTRLR2.ADDRcntr.IEEE	ADDRcntr	[Library]
IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.RAM_CTRLR2.RAM_CTRLR2::ar_RAM_CTRLR2.MUX2.IEEE	MUX2	[Library]
IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.MAC_CONTROLER.IEEE	MAC_CONTROLER	[Library]
IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.Multiplier.IEEE	Multiplier	[Library]
IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.Adder.IEEE	Adder	[Library]
IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.MAC_REG.IEEE	MAC_REG	[Library]
IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.MAC_MUX.IEEE	MAC_MUX	[Library]
IIR_CEL_STATE	ar_IIR_CEL_CTRLR	[Signal]
iir_filter	APB_IIR_CEL	[Package]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.iir_filter	RAM_CTRLR2	[Package]
IN1	MUX2	[Port]
IN2	MUX2	[Port]
INA1	MAC_MUX	[Port]
INA2	MAC_MUX	[Port]
INB1	MAC_MUX	[Port]
INB2	MAC_MUX	[Port]
initial_VALUE	REG	[Generic]
RAM_CTRLR2.Input_SZ	MUX2	[Generic]
ALU.Input_SZ	MAC_MUX2	[Generic]
RAM_CTRLR2.Input_SZ_1	RAM_CTRLR2	[Generic]
ALU.Input_SZ_1	ALU	[Generic]
Input_SZ_2	ALU	[Generic]
Input_SZ_A	MAC	[Generic]
MAC::ar_MAC.Multiplier.Input_SZ_A	Multiplier	[Generic]
MAC::ar_MAC.Adder.Input_SZ_A	Adder	[Generic]
MAC::ar_MAC.MAC_MUX.Input_SZ_A	MAC_MUX	[Generic]
Input_SZ_B	MAC	[Generic]
MAC::ar_MAC.Multiplier.Input_SZ_B	Multiplier	[Generic]
MAC::ar_MAC.Adder.Input_SZ_B	Adder	[Generic]
MAC::ar_MAC.MAC_MUX.Input_SZ_B	MAC_MUX	[Generic]
Logic_en	ALU	[Generic]
lpp	APB_IIR_CEL	[Library]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.RAM_CTRLR2.lpp	RAM_CTRLR2	[Library]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.RAM_CTRLR2.RAM_CTRLR2::ar_RAM_CTRLR2.ADDRcntr.lpp	ADDRcntr	[Library]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.RAM_CTRLR2.RAM_CTRLR2::ar_RAM_CTRLR2.MUX2.lpp	MUX2	[Library]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.MAC_CONTROLER.lpp	MAC_CONTROLER	[Library]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.Multiplier.lpp	Multiplier	[Library]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.Adder.lpp	Adder	[Library]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.MAC_REG.lpp	MAC_REG	[Library]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.MAC_MUX.lpp	MAC_MUX	[Library]
lpp_amba	APB_IIR_CEL	[Package]
MAC_CONTROLER1	ar_MAC	[Component Instantiation]
MAC_MUL_ADD	MAC	[Port]
MAC_MUX2_inst	ar_MAC	[Component Instantiation]
MACinst	ar_ALU	[Component Instantiation]
MACMUX2_sel	MAC_CONTROLER	[Port]
MACMUX2sel	ar_MAC	[Signal]
MACMUX2sel_D	ar_MAC	[Signal]
MACMUX2sel_D_D	ar_MAC	[Signal]
MACMUX2selREG	ar_MAC	[Component Instantiation]
MACMUX2selREG2	ar_MAC	[Component Instantiation]
MACMUX_inst	ar_MAC	[Component Instantiation]
MACMUX_sel	MAC_CONTROLER	[Port]
MACMUXsel	ar_MAC	[Signal]
MACMUXsel_D	ar_MAC	[Signal]
MACMUXselREG	ar_MAC	[Component Instantiation]
Mem_use	APB_IIR_CEL	[Generic]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.Mem_use	RAM_CTRLR2	[Generic]
MULT	MAC_CONTROLER	[Port]
mult	ar_MAC	[Signal]
Multiplier.mult	Multiplier	[Port]
Multiplieri_nst	ar_MAC	[Component Instantiation]
MULTout	ar_MAC	[Signal]
MULTout_D	ar_MAC	[Signal]
MULToutREG	ar_MAC	[Component Instantiation]
MUX2_inst1	ar_RAM_CTRLR2	[Component Instantiation]
MUX2_inst2	ar_RAM_CTRLR2	[Component Instantiation]
numeric_std	APB_IIR_CEL	[Package]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.RAM_CTRLR2.numeric_std	RAM_CTRLR2	[Package]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.RAM_CTRLR2.RAM_CTRLR2::ar_RAM_CTRLR2.RAM.numeric_std	RAM	[Package]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.RAM_CTRLR2.RAM_CTRLR2::ar_RAM_CTRLR2.RAM_CEL.numeric_std	RAM_CEL	[Package]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.RAM_CTRLR2.RAM_CTRLR2::ar_RAM_CTRLR2.ADDRcntr.numeric_std	ADDRcntr	[Package]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.RAM_CTRLR2.RAM_CTRLR2::ar_RAM_CTRLR2.MUX2.numeric_std	MUX2	[Package]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.MAC_CONTROLER.numeric_std	MAC_CONTROLER	[Package]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.Multiplier.numeric_std	Multiplier	[Package]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.Adder.numeric_std	Adder	[Package]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.MAC_REG.numeric_std	MAC_REG	[Package]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.MAC_MUX.numeric_std	MAC_MUX	[Package]
OP1	ALU	[Port]
ALU::ar_ALU.MAC::ar_MAC.Multiplier.OP1	Multiplier	[Port]
ALU::ar_ALU.MAC::ar_MAC.Adder.OP1	Adder	[Port]
OP1_D	ar_MAC	[Signal]
OP1_D_Resz	ar_MAC	[Signal]
OP1REG	ar_MAC	[Component Instantiation]
OP2	ALU	[Port]
ALU::ar_ALU.MAC::ar_MAC.Multiplier.OP2	Multiplier	[Port]
ALU::ar_ALU.MAC::ar_MAC.Adder.OP2	Adder	[Port]
OP2_D	ar_MAC	[Signal]
OP2_D_Resz	ar_MAC	[Signal]
OP2REG	ar_MAC	[Component Instantiation]
OUTA	MAC_MUX	[Port]
OUTB	MAC_MUX	[Port]
paddr	APB_IIR_CEL	[Generic]
pconfig	AR_APB_IIR_CEL	[Constant]
pindex	APB_IIR_CEL	[Generic]
pirq	APB_IIR_CEL	[Generic]
pmask	APB_IIR_CEL	[Generic]
PROCESS_10(clk, reset)	ar_IIR_CEL_CTRLR	[Process]
PROCESS_11(RWclk, reset)	DEF_ARCH	[Process]
PROCESS_12(RWclk, reset)	ar_RAM_CEL	[Process]
PROCESS_15(clk, reset)	ar_Adder	[Process]
PROCESS_16(clk, reset)	ar_ADDRcntr	[Process]
PROCESS_18(clk, reset)	ar_MAC_REG	[Process]
PROCESS_19(clk, reset)	ar_Multiplier	[Process]
PROCESS_20(clk, reset)	ar_REG	[Process]
PROCESS_7(rst, sample_clk)	AR_APB_IIR_CEL	[Process]
PROCESS_8(rst, clk)	AR_APB_IIR_CEL	[Process]
RAM_CTRLR2.ADDRcntr.Q	ADDRcntr	[Port]
RAM_CTRLR2.REG.Q	REG	[Port]
ALU.Q	MAC_REG	[Port]
r	AR_APB_IIR_CEL	[Signal]
RADDR	ar_RAM_CTRLR2	[Signal]
RAM.RADDR	RAM	[Port]
RAM_CEL.RADDR	RAM_CEL	[Port]
RAM_CTRLR2inst	ar_IIR_CEL_CTRLR	[Component Instantiation]
RAM_sample_in	ar_IIR_CEL_CTRLR	[Signal]
RAM_sample_in_bk	ar_IIR_CEL_CTRLR	[Signal]
RAM_sample_out	ar_IIR_CEL_CTRLR	[Signal]
RAM.RAMarray	DEF_ARCH	[Signal]
RAM_CEL.RAMarray	ar_RAM_CEL	[Signal]
RAM.RAMarrayT	DEF_ARCH	[Type]
RAM_CEL.RAMarrayT	ar_RAM_CEL	[Type]
RAMblk	ar_RAM_CTRLR2	[Component Instantiation]
RAMblk	ar_RAM_CTRLR2	[Component Instantiation]
RD	ar_RAM_CTRLR2	[Signal]
RAM.RD	RAM	[Port]
RAM_CEL.RD	RAM_CEL	[Port]
RAM.RD_int	DEF_ARCH	[Signal]
RAM_CEL.RD_int	ar_RAM_CEL	[Signal]
Rdata	AR_APB_IIR_CEL	[Signal]
Read	ar_IIR_CEL_CTRLR	[Signal]
RAM_CTRLR2.Read	RAM_CTRLR2	[Port]
reg	ar_ADDRcntr	[Signal]
Multiplier.REG	ar_Multiplier	[Signal]
Adder.REG	ar_Adder	[Signal]
regs_in	IIR_CEL_FILTER	[Port]
regs_out	IIR_CEL_FILTER	[Port]
REN	ar_RAM_CTRLR2	[Signal]
RAM.REN	RAM	[Port]
RAM_CEL.REN	RAM_CEL	[Port]
RAM_CTRLR2.RES	MUX2	[Port]
ALU.RES	ALU	[Port]
ALU.ALU::ar_ALU.MAC::ar_MAC.Multiplier.RES	Multiplier	[Port]
ALU.ALU::ar_ALU.MAC::ar_MAC.Adder.RES	Adder	[Port]
RES1	MAC_MUX2	[Port]
RES2	MAC_MUX2	[Port]
RESADD	ar_Adder	[Signal]
reset	IIR_CEL_FILTER	[Port]
IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.RAM_CTRLR2.reset	RAM_CTRLR2	[Port]
IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.RAM_CTRLR2.RAM_CTRLR2::ar_RAM_CTRLR2.ADDRcntr.reset	ADDRcntr	[Port]
IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.Multiplier.reset	Multiplier	[Port]
IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.Adder.reset	Adder	[Port]
IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.MAC_REG.reset	MAC_REG	[Port]
RAM.RESET	RAM	[Port]
RAM_CEL.RESET	RAM_CEL	[Port]
RESMULT	ar_Multiplier	[Signal]
REVISION	AR_APB_IIR_CEL	[Constant]
rst	APB_IIR_CEL	[Port]
RAM.RWCLK	RAM	[Port]
RAM_CEL.RWCLK	RAM_CEL	[Port]
sample_clk	APB_IIR_CEL	[Port]
sample_clk_out	APB_IIR_CEL	[Port]
sample_clk_out_R	AR_APB_IIR_CEL	[Signal]
sample_in	APB_IIR_CEL	[Port]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.sample_in	RAM_CTRLR2	[Port]
sample_in_BUFF	ar_IIR_CEL_CTRLR	[Signal]
sample_out	APB_IIR_CEL	[Port]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.sample_out	RAM_CTRLR2	[Port]
sample_out_BUFF	ar_IIR_CEL_CTRLR	[Signal]
Sample_SZ	APB_IIR_CEL	[Generic]
sampleBuffT	ar_IIR_CEL_CTRLR	[Type]
sampleVect	ar_IIR_CEL_CTRLR	[Subtype]
RAM_CTRLR2.sel	MUX2	[Port]
ALU.MAC_MUX.sel	MAC_MUX	[Port]
ALU.MAC_MUX2.sel	MAC_MUX2	[Port]
RAM_CTRLR2.size	REG	[Generic]
ALU.size	MAC_REG	[Generic]
smp_cnt	AR_APB_IIR_CEL	[Signal]
smpl_clk_old	ar_IIR_CEL_CTRLR	[Signal]
std_logic_1164	APB_IIR_CEL	[Package]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.RAM_CTRLR2.std_logic_1164	RAM_CTRLR2	[Package]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.RAM_CTRLR2.RAM_CTRLR2::ar_RAM_CTRLR2.RAM.std_logic_1164	RAM	[Package]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.RAM_CTRLR2.RAM_CTRLR2::ar_RAM_CTRLR2.RAM_CEL.std_logic_1164	RAM_CEL	[Package]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.RAM_CTRLR2.RAM_CTRLR2::ar_RAM_CTRLR2.ADDRcntr.std_logic_1164	ADDRcntr	[Package]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.RAM_CTRLR2.RAM_CTRLR2::ar_RAM_CTRLR2.MUX2.std_logic_1164	MUX2	[Package]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.MAC_CONTROLER.std_logic_1164	MAC_CONTROLER	[Package]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.Multiplier.std_logic_1164	Multiplier	[Package]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.Adder.std_logic_1164	Adder	[Package]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.MAC_REG.std_logic_1164	MAC_REG	[Package]
APB_IIR_CEL::AR_APB_IIR_CEL.IIR_CEL_FILTER::ar_IIR_CEL_FILTER.IIR_CEL_CTRLR::ar_IIR_CEL_CTRLR.ALU.ALU::ar_ALU.MAC::ar_MAC.MAC_MUX.std_logic_1164	MAC_MUX	[Package]
stdlib	APB_IIR_CEL	[Package]
SVG_ADDR	ar_IIR_CEL_CTRLR	[Signal]
RAM_CTRLR2.SVG_ADDR	RAM_CTRLR2	[Port]
virg_pos	ar_IIR_CEL_FILTER	[Signal]
virgPos	APB_IIR_CEL	[Generic]
WADDR	ar_RAM_CTRLR2	[Signal]
RAM.WADDR	RAM	[Port]
RAM_CEL.WADDR	RAM_CEL	[Port]
WADDR_back	ar_RAM_CTRLR2	[Signal]
WADDR_back_D	ar_RAM_CTRLR2	[Signal]
WADDR_backreg	ar_RAM_CTRLR2	[Component Instantiation]
WADDR_backreg2	ar_RAM_CTRLR2	[Component Instantiation]
WADDR_D	ar_RAM_CTRLR2	[Signal]
WADDR_sel	ar_IIR_CEL_CTRLR	[Signal]
RAM_CTRLR2.WADDR_sel	RAM_CTRLR2	[Port]
WD	ar_RAM_CTRLR2	[Signal]
RAM.WD	RAM	[Port]
RAM_CEL.WD	RAM_CEL	[Port]
WD_D	ar_RAM_CTRLR2	[Signal]
WD_sel	ar_IIR_CEL_CTRLR	[Signal]
RAM_CTRLR2.WD_sel	RAM_CTRLR2	[Port]
WDRreg	ar_RAM_CTRLR2	[Component Instantiation]
WEN	ar_RAM_CTRLR2	[Signal]
RAM.WEN	RAM	[Port]
RAM_CEL.WEN	RAM_CEL	[Port]
Write	ar_IIR_CEL_CTRLR	[Signal]
RAM_CTRLR2.Write	RAM_CTRLR2	[Port]