- c -

• Capture : ar_APB_UART , BaudGen , UART
• Cels_count : APB_IIR_CEL , FILTERcfg , IIR_CEL_CTRLR , IIR_CEL_FILTER
• CFGM_completed : Behavioral
• CFGM_Enable : Behavioral
• CFGM_LCD_DATA : Behavioral
• CFGM_LCD_E : Behavioral
• CFGM_LCD_RS : Behavioral
• CFGM_LCD_RW : Behavioral
• chanelCnt : ar_FilterCTRLR
• ChanelCount : AD7688_drvr , AD7688_spi_if , ADS7886_drvr , lpp_apb_ad_conv
• ChanelsCNT : FILTER , FILTERcfg
• ChanelsCount : APB_IIR_CEL , IIR_CEL_CTRLR , IIR_CEL_FILTER
• ClearDSPLY : LCD_16x2_CFG
• clk : APB_MULTI_DIODE , APB_SIMPLE_DIODE , apb_lcd_ctrlr , APB_CNA , ar_CNA_TabloC , FRAME_CLK_GEN , Serialize , Systeme_Clock , LCD_16x2_DRIVER , APB_FIFO , APB_FifoRead , LCD_16x2_ENGINE , APB_FifoWrite , ApbDriver , LCD_2x16_DRIVER , Fifo_Read , Fifo_Write , LCD_CLK_GENERATOR , Link_Reg , Top_FIFO , AMBA_LCD_16x2_DRIVER , Top_FifoRead , Top_FifoWrite , APB_IIR_CEL , APB_UART , BaudGen , FILTER , Shift_REG , UART , FILTER_RAM_CTRLR , FilterCTRLR , IIR_CEL_CTRLR , IIR_CEL_FILTER , RAM_CTRLR2 , ar_TestbenshMAC , APB_FFT , Flag_Extremum , Adder , ADDRcntr , ALU , Clk_divider , MAC , MAC_REG , Multiplier , REG , RShifter , ar_TestbenshALU , AD7688_drvr , AD7688_spi_if , ADS7886_drvr , lpp_apb_ad_conv
• CLK0 : Behavioral
• clk_1us : Behavioral , LCD_CLK_GENERATOR
• clk_1us_int : ar_LCD_CLK_GENERATOR
• clk_1us_reg : Behavioral
• clk_1usTRIGER : ar_LCD_CLK_GENERATOR
• clk_divided : Clk_divider
• Clk_divider : general_purpose
• clk_int : ar_Clk_divider , ar_AD7688_drvr , ar_ADS7886_drvr
• clk_inv : ar_FilterCTRLR
• clk_TRIGER : ar_Clk_divider
• clkdivider : ar_AD7688_drvr , ar_ADS7886_drvr , ar_lpp_apb_ad_conv
• CLKINT : ar_CNA_TabloC
• CLKINT_0 : ar_CNA_TabloC
• CLKINT_1 : ar_CNA_TabloC
• clkkHz : AD7688_drvr , ADS7886_drvr , lpp_apb_ad_conv
• clock : CNA_TabloC
• clockint : ar_Systeme_Clock
• clr : Adder , ADDRcntr
• clr_mac : iir_filter , ar_TestbenshALU
• clr_MAC : ar_ALU , MAC
• clr_MAC_D : ar_MAC
• clr_MAC_D_D : ar_MAC
• clr_MACREG1 : ar_MAC
• clr_MACREG2 : ar_MAC
• clrMAC : ar_TestbenshMAC
• CMD : Behavioral , LCD_16x2_ENGINE
• CMD_Data : amba_lcd_16x2_ctrlr
• CMD_Flag : ar_LCD_16x2_ENGINE
• CNA_Cfg : ar_APB_CNA
• CNA_ctrlr_Reg : ar_APB_CNA
• CNA_Data : ar_APB_CNA
• CNA_TabloC : lpp_cna
• cnt : RShifter
• cnv : AD7688_spi_if
• CNV : lpp_ad_conv
• cnv_int : ar_ADS7886_drvr , ar_AD7688_drvr
• cnv_reg : ar_AD7688_spi_if
• Coef : ar_FILTER
• coef : FilterCTRLR
• Coef_SZ : APB_IIR_CEL , IIR_CEL_FILTER , IIR_CEL_CTRLR , FILTERcfg
• CoefCelT : AR_APB_IIR_CEL , ar_IIR_CEL_CTRLR
• CoefCntPerCel : IIR_CEL_FILTER , APB_IIR_CEL , IIR_CEL_CTRLR
• coefs : IIR_CEL_FILTER , IIR_CEL_CTRLR
• CoefsReg : ar_IIR_CEL_CTRLR , AR_APB_IIR_CEL
• CoefsRegT : AR_APB_IIR_CEL , ar_IIR_CEL_CTRLR
• CoefTblT : ar_IIR_CEL_CTRLR , AR_APB_IIR_CEL
• COM0 : ar_APB_UART
• config : Top_FifoRead , iir_filter , Top_FIFO , iir_filter , Top_FifoWrite
• ConfigModule : Behavioral
• ConfigTbl : ar_LCD_16x2_ENGINE
• CONVERTER : ar_APB_CNA
• Convertisseur_config : CNA_TabloC
• convTrigger : ar_AD7688_drvr , ar_ADS7886_drvr
• CoreFFT : lpp_fft
• count : ADDRcntr , ar_IIR_CEL_CTRLR , ar_Gene_SYNC , RAM_CTRLR2
• Counter : Behavioral
• counter : lpp_fft
• countint : ar_Systeme_Clock
• CPT : Behavioral
• cpt : ar_BaudGen
• cpt1 : ar_LCD_CLK_GENERATOR , ar_Clk_divider
• CPT_ended : ar_Serialize
• CptBits : ar_Shift_REG
• CptBits_flag : ar_Shift_REG
• CptBits_flag_reg : ar_Shift_REG
• CptBits_trig : ar_Shift_REG
• ctrl : ALU , MAC_CONTROLER , ar_TestbenshALU
• CTRL_Reg : Behavioral , ar_lpp_apb_ad_conv
• CTRLR : ar_IIR_CEL_FILTER
• curentCel : ar_IIR_CEL_CTRLR
• curentChan : ar_IIR_CEL_CTRLR
• CursorOFF : LCD_16x2_CFG
• CursorON : LCD_16x2_CFG